1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device, specifically to a manufacturing method of a semiconductor device having a MOS transistor and a diffused resistor formed on the same semiconductor substrate.
2. Description of the Related Art
A Bi-MOS IC has been known as a semiconductor device used in a circuit for a receiver such as a television. The Bi-MOS IC is a semiconductor device in which, for example, a MOS transistor and a diffused resistor layer are formed on a single semiconductor substrate together with a bipolar transistor capable of driving a large current. The MOS transistor usually has a sidewall spacer on a sidewall of its gate electrode. The diffused resistor layer is formed by doping the semiconductor substrate with low concentration impurities and used for a purpose such as voltage reduction required in the circuit.
Next, a manufacturing method of a semiconductor device according to the prior art applicable to the Bi-MOS IC will be explained, referring to FIGS. 8-12, which are cross-sectional views showing the manufacturing method of the semiconductor device according the prior art. Although various electronic devices including a bipolar transistor are formed on a P-type semiconductor substrate 10, FIGS. 8–12 show only a region in which a MOS transistor 20 and a diffused resistor layer 30 are formed.
At first, an N-type well 11 is formed on the P-type semiconductor substrate 10, as shown in FIG. 8. Device isolation layers 12 are formed by LOCOS (Local Oxidation of Silicon) on the N-type well 11 around a periphery of a region in which the diffused resistor layer 30 is to be formed. Then a gate insulation film 21 made of silicon oxide, for example, is formed on the entire surface of the N-type well 11, except for the device isolation layers 12.
Next, a gate electrode 22 is formed on the gate insulation film 21 on a portion of a region separated with the device isolation layer 12 from the region in which the diffused resistor layer 30 is to be formed, as shown in FIG. 9. Then, a photoresist layer 40 is formed to have an opening 40m above the region in which the diffused resistor layer 30 is to be formed by exposure using a photomask (not shown) and development. Using the photoresist layer 40 as a mask, the region of the N-type well 11 is doped with low concentration P-type impurities such as boron to form a P−-type diffusion layer. The P−-type diffusion layer makes the diffused resistor layer 30.
After removing the photoresist layer 40, a CVD (Chemical Vapor Deposition) insulation film 23 made of a silicon oxide film, for example, is formed by CVD over the entire surface of the N-type well 11, as shown in FIG. 10.
The CVD insulation film 23 is anisotropically etched to form a sidewall spacer 23s on each sidewall of the gate electrode 22, as shown in FIG. 11.
Then, the N-type well 11 and the P−-type diffusion layer are selectively doped with high concentration P-type impurities using a photomask (not shown) to form a source layer 24s and a drain layer 24d of the MOS transistor 20 and P+-type layers 31 which serve as contact regions to the diffused resistor layer 30. The MOS transistor 20 having a sidewall spacer 23s on each sidewall of its gate electrode 22 and the diffused resistor layer 30 are formed on the same P-type semiconductor substrate 10 through the manufacturing method described above. Related descriptions on the technologies mentioned above are provided, for example, in Japanese Patent No. 3143366.
With the manufacturing method of the semiconductor device according to the prior art, however, a surface of the diffused resistor layer 30 suffers damage such as crystal defect by over-etching in a process step of the anisotropic etching of the CVD insulation film 23 to form the sidewall spacers 23s. As a result, a variation in a status of the diffused resistor layer 30 is increased and operational characteristics of the diffused resistor layer 30 are deteriorated.
That is, when the over-etching mentioned above causes the damage to the diffused resistor layer 30, especially to a region in the diffused resistor layer close to the border with the device isolation layer 12, there arise a lot of leakage paths through which leakage current flows into the N-type well 11 (Refer to an arrow in FIG. 12.). In particular, when a bipolar transistor (not shown) formed on the P-type semiconductor substrate 10 operates long period of time, Joule heat caused by the operation heats up the diffused resistor layer 30 formed on the same P-type semiconductor substrate 10, further increasing the leakage current. It results in the deterioration of operational characteristics of the semiconductor device. Although the over-etching causes the damage to the entire surface, the region into which high concentration impurities are injected in a subsequent process step shows almost no increase in the leakage current because of the higher impurity concentration in the region compared with the other region into which low concentration impurities are injected.